This is called a root module. Icarus Verilog chooses as roots There can be more than one root all the modules that are not instantiated by other modules. If there are no such modules, the compiler will not be able to choose any root, and the designer must use the "-s root " switch to identify the root module, like this:. If there are multiple candidate roots, all of them will be elaborated.
The compiler will do this even if there are many root modules that you do not intend to simulate, or that have no effect on the simulation. This can happen, for example, if you include a source file that has multiple modules, but are only really interested in some of them.
The "-s" flag identifies a specific root module and also turns off the automatic search for other root modules. You can use this feature to prevent instantiation of unwanted roots. As designs get even larger, they become spread across many dozens or even hundreds of files. When designs are that complex, more advanced source code management techniques become necessary. These are described in later chapters, along with other advanced design management techniques supported by Icarus Verilog.
Icarus Verilog Explore. Wiki Content. Explore Wikis Community Central. Register Don't have an account? Getting Started. Edit source History Talk 1. While Icarus Verilog is not literally part of the gEDA project, we cooperate and try to support each other. Icarus Verilog users are often gEDA users as well.
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What Is Icarus Verilog? Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog IEEE into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. For synthesis, the compiler generates netlists in the desired format.
Where is Icarus Verilog? Home Welcome to the home page for Icarus Verilog. Updates to the stable release may be made from time to time to fix problems, but there should be no compatibility issues within this version series. This will continue to be maintained until rendered obsolete by a new stable release.
One of the most well-known languages of this kind is Verilog and it has know extensive usage in simulations and verifications, as it set the standards on the market. This software solution is prepared to perform batch simulations as well and for this purpose it will create a particular kind of intermediate form that executes by means of the 'wp' command and thus it is known under the name of 'wp assembly'.
In case it is used for synthesis functions, Icarus Verilog is able to generate netlists of various types. Complying with the IEEE Std standard for Verilog hardware description language, this compiler can be used to put together intricate design descriptions and parse them as well.
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